The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Apr. 08, 2016
Applicant:
Infinera Corporation, Annapolis Junction, MD (US);
Inventors:
Saurabh Pandey, Bangalore, IN;
Saratchandar Adayapalam Viswanathan, Bangalore, IN;
Vinay Khana, Bangalore, IN;
Assignee:
Infinera Corporation, Sunnyvale, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 14/08 (2006.01); H04B 10/032 (2013.01);
U.S. Cl.
CPC ...
H04J 14/08 (2013.01); H04B 10/032 (2013.01);
Abstract
Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.