The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Dec. 28, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-Do, KR;

Inventors:

Chang-Soo Pyon, Seongnam-si, KR;

Ju-Hee Hyeon, Suwon-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/3223 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01);
Abstract

A display panel includes a substrate including a display area, a peripheral area and a buffer area disposed between the display area and the peripheral area. The display panel further includes a switching element disposed in the display area. The switching element includes an active pattern, a gate electrode overlapping the active pattern, a source electrode connecting with the active pattern, and a drain electrode spaced apart from the source electrode. The display panel further includes a power supply line disposed in the peripheral area and disposed on a same layer as the source electrode and the drain electrode. The display panel additionally includes a power connecting line disposed in the buffer area and connecting the switching element to the power supply line. The display panel further includes a dummy active pattern disposed in the buffer area and overlapping the power connecting line.


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