The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Apr. 25, 2017
Applicant:

Tela Innovations, Inc., Los Gatos, CA (US);

Inventors:

Michael C. Smayling, Fremont, CA (US);

Scott T. Becker, Scotts Valley, CA (US);

Assignee:

Tela Innovations, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/00 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 2217/12 (2013.01);
Abstract

A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.


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