The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jun. 06, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Byoung-Sung You, Gyeonggi-do, KR;

Jae-Hyoung Ko, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 12/02 (2006.01); G11C 16/10 (2006.01); G11C 16/28 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G06F 12/0253 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); G06F 2212/7205 (2013.01);
Abstract

A memory device includes a pass/fail check circuit configured to compare the number of memory cells, which are verified as being a program fail based on a result of verifying program operations of a first group of memory cells of a plurality of memory cells, with a first reference bit number, and to check whether the first group of memory cells is a pass or fail and a control circuit configured to control the pass/fail check circuit to recheck whether the first group of memory cells is the pass or fail based on a second reference bit number smaller than the first reference bit number when the first group of memory cells is found to be the pass based on a result of a pass/fail check operation of the pass/fail check circuit.


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