The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jun. 23, 2015
Applicant:

Synaptics Japan Gk, Tokyo, JP;

Inventors:

Masashi Takata, Tokyo, JP;

Shigeki Ueda, Tokyo, JP;

Norihiro Enomoto, Tokyo, JP;

Assignee:

Synaptics Japan GK, Nakano, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3696 (2013.01); G09G 3/3685 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0297 (2013.01); G09G 2370/08 (2013.01);
Abstract

The voltage transmission circuit includes: a multiplexer for transmitting positive and negative voltages ranging +VDD to −VDD selectively; and a demultiplexer for receiving the positive and negative voltages and output them at positive and negative outputs. The voltage transmission circuit is arranged by use of elements each having a withstand voltage of which the absolute value is not 2|VDD|, but |VDD|. While transmitting positive voltages, the multiplexer is configured not to be applied by negative voltages, the multiplexer and demultiplexer are controlled by signals each having a potential of 0 V to +VDD, and the demultiplexer outputs the positive voltages at the positive output. While transmitting negative voltages, the multiplexer is configured not to be applied by positive voltages, the multiplexer and the demultiplexer are controlled by signals each having a potential of −VDD to 0 V, and the demultiplexer outputs the negative voltages at the negative output.


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