The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Apr. 10, 2017
Applicant:
Sharp Kabushiki Kaisha, Osaka, JP;
Inventors:
Masahiro Tomida, Osaka, JP;
Naoki Ueda, Osaka, JP;
Assignee:
SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); G02F 1/1362 (2006.01); G02F 1/133 (2006.01); G02F 1/1343 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 27/32 (2006.01); G02F 1/1345 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G02F 1/1368 (2013.01); G02F 1/13306 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/3276 (2013.01); H01L 29/24 (2013.01); H01L 29/41733 (2013.01); H01L 29/42356 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H05K 999/99 (2013.01); G02F 1/13454 (2013.01); G02F 1/133345 (2013.01); G02F 2001/133302 (2013.01); G02F 2201/123 (2013.01); G02F 2202/10 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01); G09G 2330/021 (2013.01); H01L 29/78696 (2013.01);
Abstract
An active matrix substrate includes a display region in which a plurality of pixels are provided and a frame region lying outside the display region. The frame region includes a plurality of peripheral circuit TFTs which are supported by a substrate and which are constituents of a driving circuit. Each of the plurality of peripheral circuit TFTs includes a gate electrode, an oxide semiconductor layer arranged so as to at least partially extend over the gate electrode but to be insulated from the gate electrode, and source and drain electrodes connected with the oxide semiconductor layer.