The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Sep. 03, 2015
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., San Jose, CA (US);

Inventors:

Rajendran Vishwanathan, San Jose, CA (US);

Nagarajan Subramaniyan, San Jose, CA (US);

Jeffrey Michael Dodson, Portland, OR (US);

Jack Regula, Chapel Hill, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/16 (2013.01); G06F 9/5077 (2013.01); G06F 2009/45579 (2013.01);
Abstract

Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.


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