The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Sep. 03, 2014
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Masanao Yamaoka, Tokyo, JP;

Chihiro Yoshimura, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06N 7/00 (2006.01); G06N 99/00 (2010.01);
U.S. Cl.
CPC ...
G06F 3/0655 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06N 7/005 (2013.01); G06N 99/002 (2013.01);
Abstract

A semiconductor integrated circuit apparatusis used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatusincludes plural spin cellsthat are connected with each other. Here, each spin cellincludes: a memory cell(N) for memorizing a spin value; a computing circuitfor computing interactions among the plural spin cells that are connected with each other; a memory circuitfor holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell(N) included in each spin cell


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