The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jan. 13, 2016
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Narendhiran Chinnaanangur Ravimohan, Bangalore, IN;

Muralitharan Jayaraman, Bangalore, IN;

Vijay Sivasankaran, Bangalore, IN;

Krishnamurthy Dhakshinamurthy, Bangalore, IN;

Arun Thandapani, Bangalore, IN;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0632 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.


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