Cycle deterministic functional testing of a chip with asynchronous clock domains

Abstract

Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.