The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Feb. 21, 2017
Applicant:

The Boeing Company, Chicago, IL (US);

Inventors:

Andrew George Laquer, Tustin, CA (US);

Dean L Araki, Redondo Beach, CA (US);

Pohan Yang, Cypress, CA (US);

Assignee:

The Boeing Company, Chicago, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/14 (2006.01); H03F 1/30 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 23/522 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01); H01L 23/66 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H03F 1/30 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/7787 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6644 (2013.01); H01L 2223/6661 (2013.01); H01L 2223/6683 (2013.01); H03F 2200/447 (2013.01); H03F 2200/451 (2013.01); H03F 2200/543 (2013.01);
Abstract

The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system may include a plurality of high electron mobility transistors disposed on a first substrate. A first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate. The system also includes a plurality of second level interconnects disposed on a second substrate. A second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects. The first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides an amplified output signal via at least one of the first level interconnects or the second level interconnects.


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