The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Dec. 15, 2015
Applicant:

Gachon University of Industry-academic Cooperation Foundation, Seongnam-si, Gyeonggi-do, KR;

Inventors:

Seongjae Cho, Seoul, KR;

Youngmin Kim, Seongnam-si, KR;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/302 (2006.01); H01L 21/324 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 21/0262 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02694 (2013.01); H01L 21/302 (2013.01); H01L 29/401 (2013.01); H01L 29/66757 (2013.01); H01L 21/02667 (2013.01);
Abstract

A junctionless field-effect transistor is provided and has an ultra-thin low-crystalline silicon channel. A fabrication method thereof also is provided for enabling greatly improved economics by significantly reducing the process costs while having electrical characteristics similar to those of the one formed on an SOI substrate by source/channel/drain regions formed in a junctionless ultra-thin low-crystalline silicon layer that has lower crystallinity than that of single-crystal silicon and that has a thickness of 20 nm or less on a bulk silicon substrate instead of an expensive SOI substrate.


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