The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Sep. 13, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Naoharu Shimomura, Meguro, JP;

Hiroaki Yoda, Kawasaki, JP;

Tadaomi Daibou, Yokohama, JP;

Yuuzo Kamiguchi, Yokohama, JP;

Yuichi Ohsawa, Yokohama, JP;

Tomoaki Inokuchi, Yokohama, JP;

Satoshi Shirotori, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/02 (2006.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); H01L 43/02 (2013.01);
Abstract

A magnetic memory of an embodiment includes: a first nonmagnetic layer including a first and second faces; a first and second wirings disposed on a side of the first face; a third wiring disposed on a side of the second face; a first transistor, one of the source and the drain being connected to the first wiring, the other one being connected to the first nonmagnetic layer; a second transistor, one of source and drain being connected to the second wiring, the other one being connected to the first nonmagnetic layer; a magnetoresistive element disposed between the first nonmagnetic layer and the third wiring, a first terminal of the magnetoresistive element being connected to the first nonmagnetic layer; and a third transistor, one of source and drain of the third transistor being connected to the second terminal, the other one being connected to the third wiring.


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