The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Jun. 27, 2017
Applicants:

Jaeick Son, Hwaseong-si, KR;

Sunghoon Kim, Seongnam-si, KR;

Inventors:

Jaeick Son, Hwaseong-si, KR;

Sunghoon Kim, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 47/00 (2006.01); H01L 27/11573 (2017.01); G11C 13/00 (2006.01); G11C 16/30 (2006.01); H01L 23/528 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/24 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); G11C 13/0038 (2013.01); G11C 16/30 (2013.01); H01L 23/5286 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 29/94 (2013.01);
Abstract

A three-dimensional semiconductor device includes a semiconductor substrate including a cell array region and a peripheral circuit region, an electrode structure including electrodes vertically stacked on the cell array region, a MOS capacitor on the peripheral circuit region, an interlayer dielectric layer covering the electrode structure and the MOS capacitor, first and second power lines spaced apart from each other in a first direction and extending in a second direction on the interlayer dielectric layer, first lower plugs connected to the first power line and a first terminal of the MOS capacitor, and second lower plugs connected to the second power line to a second terminal of the MOS capacitor. The second power line is on one of the first lower plugs that is adjacent to some of the second lower plugs in one of the first and second directions.


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