The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Sep. 25, 2017
Applicant:
Sii Semiconductor Corporation, Chiba-shi, Chiba, JP;
Inventor:
Kazuhiro Tsumura, Chiba, JP;
Assignee:
ABLIC Inc., , JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H01L 27/11521 (2017.01); H01L 27/112 (2006.01); H01L 21/8228 (2006.01); H01L 29/423 (2006.01); G11C 17/18 (2006.01); H01L 29/94 (2006.01); G11C 16/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/02 (2013.01); G11C 17/18 (2013.01); H01L 21/8228 (2013.01); H01L 27/11206 (2013.01); H01L 29/42324 (2013.01); H01L 29/94 (2013.01);
Abstract
Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.