The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Nov. 30, 2016
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventor:
Hartmud Terletzki, Poughkeepsie, NY (US);
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 28/40 (2013.01); H01L 28/65 (2013.01); H01L 29/0653 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01);
Abstract
A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a substrate contact region coupled to a body region. A shallow trench isolation (STI) area is formed in a major surface of the semiconductor substrate in between the active transistor region and the substrate contact region. The method further includes at least partially burying at least one capacitor in the STI area.