The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Jan. 12, 2015
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

James Zhao, San Francisco, CA (US);

Javier Alejandro Salcedo, North Billerica, MA (US);

Assignee:

ANALOG DEVICES, INC., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8222 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H03K 17/567 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 21/8222 (2013.01); H01L 28/20 (2013.01); H01L 29/0638 (2013.01); H01L 29/1095 (2013.01); H01L 29/861 (2013.01); H03K 17/567 (2013.01); H01L 29/0649 (2013.01);
Abstract

Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.


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