The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
May. 10, 2017
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventors:
Po-Chun Lin, Changhua County, TW;
Chin-Lung Chu, Taoyuan, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/05 (2013.01); H01L 24/10 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/04 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05671 (2013.01); H01L 2224/10125 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/10145 (2013.01); H01L 2224/11013 (2013.01); H01L 2224/11472 (2013.01); H01L 2224/11616 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/13011 (2013.01); H01L 2224/13017 (2013.01); H01L 2224/13018 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13076 (2013.01); H01L 2224/13078 (2013.01); H01L 2224/1607 (2013.01); H01L 2224/16012 (2013.01); H01L 2224/16105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81815 (2013.01);
Abstract
A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.