The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Mar. 17, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

Christian Klewer, Dresden, DE;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76801 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 23/53238 (2013.01); H01L 29/0649 (2013.01); H01L 29/78 (2013.01);
Abstract

A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.


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