The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Jan. 09, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Alan B. Botula, Essex Junction, VT (US);

Max L. Lifson, South Burlington, VT (US);

James A. Slinkman, Montpelier, VT (US);

Theodore G. Van Kessel, Millbrook, NY (US);

Randy L. Wolf, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 21/288 (2006.01); H01L 21/3205 (2006.01); H01L 21/02 (2006.01); H01L 29/41 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3677 (2013.01); H01L 21/02178 (2013.01); H01L 21/02271 (2013.01); H01L 21/2885 (2013.01); H01L 21/32051 (2013.01); H01L 21/32053 (2013.01); H01L 21/4882 (2013.01); H01L 23/3731 (2013.01); H01L 23/3738 (2013.01); H01L 29/413 (2013.01);
Abstract

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.


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