The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Oct. 28, 2016
Applicant:

Synaptics Japan Gk, Tokyo, JP;

Inventors:

Hiroshi Morimoto, Tokyo, JP;

Kanehiro Masumitsu, Tokyo, JP;

Assignee:

Synaptics Japan GK, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01); G09G 5/00 (2006.01); G09G 5/395 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G09G 5/006 (2013.01); G09G 5/395 (2013.01); G11C 7/1045 (2013.01); G11C 7/1075 (2013.01); G11C 7/222 (2013.01);
Abstract

A buffer memory and display drive device are described herein. In one example, a buffer memory is arranged so that write and read address counters are controlled according to a wraparound method, and subjected to no reset in count value, which enables the avoidance of data destruction in a boundary portion of a block. In the buffer memory, block head addresses of the write and read address counters are managed centrally. So, even in the event of undesired change in count value, the influence thereof can be intercepted halfway. While reducing the memory capacity of the buffer memory which is supplied with data in blocks, the following are made possible: to prevent the deviation in read data owing to an undesired change in the address counter from lasting; and to prevent data, handled in blocks, from disappearing near a block boundary.


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