The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Oct. 27, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jared Barney Hertzberg, Ossining, NY (US);

Werner A. Rausch, Stormville, NY (US);

Sami Rosenblatt, White Plains, NY (US);

Rasit O. Topaloglu, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 99/00 (2010.01); H01L 27/18 (2006.01); H01L 39/22 (2006.01); H01L 39/24 (2006.01); H01G 4/008 (2006.01); H01L 39/02 (2006.01);
U.S. Cl.
CPC ...
G06N 99/002 (2013.01); H01G 4/008 (2013.01); H01L 27/18 (2013.01); H01L 39/025 (2013.01); H01L 39/223 (2013.01); H01L 39/2409 (2013.01);
Abstract

A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.


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