The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Jul. 13, 2015
Nvidia Corporation, Santa Clara, CA (US);
Gregory Frederick Diamos, San Jose, CA (US);
Richard Craig Johnson, Chapel Hill, NC (US);
Vinod Grover, Mercer Island, WA (US);
Olivier Giroux, Santa Clara, CA (US);
Jack H. Choquette, Palo Alto, CA (US);
Michael Alan Fetterman, Boxborough, MA (US);
Ajay S. Tirumala, Cupertino, CA (US);
Peter Nelson, San Francisco, CA (US);
Ronny Meir Krashinsky, San Francisco, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
A method, system, and computer program product for executing divergent threads using a convergence barrier are disclosed. A first instruction in a program is executed by a plurality of threads, where the first instruction, when executed by a particular thread, indicates to a scheduler unit that the thread participates in a convergence barrier. A first path through the program is executed by a first divergent portion of the participating threads and a second path through the program is executed by a second divergent portion of the participating threads. The first divergent portion of the participating threads executes a second instruction in the program and transitions to a blocked state at the convergence barrier. The scheduler unit determines that all of the participating threads are synchronized at the convergence barrier and the convergence barrier is cleared.