The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

May. 19, 2016
Applicant:

Tactotek Oy, Oulunsalo, FI;

Inventors:

Mikko Heikkinen, Oulu, FI;

Jarmo Sääski, Kempele, FI;

Jarkko Torvinen, Kempele, FI;

Assignee:

TACTOTEK OY, Oulunsalo, FI;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H01L 33/52 (2010.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/186 (2013.01); H01L 23/4985 (2013.01); H01L 23/5387 (2013.01); H01L 33/52 (2013.01); H01L 51/0097 (2013.01); H05K 1/0274 (2013.01); H05K 1/0298 (2013.01); H01L 2224/1319 (2013.01); H01L 2933/005 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/05 (2013.01); H05K 2201/10106 (2013.01); H05K 2201/10151 (2013.01);
Abstract

A multilayer structure for an electronic device having a flexible substrate film () for accommodating electronics (); at least one electronic component () provided on said substrate film (); and a number of conductive traces () provided on said substrate film () for electrically powering and/or connecting electronics including said at least one electronic component (), wherein at least one preferably thermoformed cover () is attached to said substrate film () on top of said at least one electronic component (), the at least one thermoformed cover () and the substrate film () accommodating the electronics () being overmolded with thermoplastic material (). The invention also relates to a method for manufacturing a multilayer structure for an electronic device.


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