The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

May. 31, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ju-Hyun Kim, Hwaseong-si, KR;

Ho-Young Kim, Seongnam-si, KR;

Se-Jung Park, Hwaseong-si, KR;

Bo-Un Yoon, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/76229 (2013.01); H01L 21/76232 (2013.01); H01L 27/0886 (2013.01); H01L 29/4238 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/7854 (2013.01);
Abstract

A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.


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