The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Dec. 02, 2016
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Sen Huang, Beijing, CN;

Xinyu Liu, Beijing, CN;

Xinhua Wang, Beijing, CN;

Ke Wei, Beijing, CN;

Qilong Bao, Beijing, CN;

Wenwu Wang, Beijing, CN;

Chao Zhao, Kessel-lo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/00 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/205 (2006.01); H01L 29/20 (2006.01); H01L 29/15 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/30621 (2013.01); H01L 29/155 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01);
Abstract

A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.


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