The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Dec. 28, 2016
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Geoffrey P. McKnight, Los Angeles, CA (US);

Brian K. Guenter, Redmond, WA (US);

Andrew Keefe, Encino, CA (US);

Neel S. Joshi, Seattle, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/372 (2011.01); H01L 27/146 (2006.01); H01L 21/304 (2006.01); H04N 5/378 (2011.01); G06T 3/40 (2006.01); H04N 5/376 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14683 (2013.01); G06T 3/4007 (2013.01); H01L 21/304 (2013.01); H01L 27/14601 (2013.01); H01L 27/14618 (2013.01); H04N 5/372 (2013.01); H04N 5/376 (2013.01); H04N 5/378 (2013.01);
Abstract

Techniques for fabricating a semiconductor die having a curved surface can include placing a substantially flat semiconductor die in a recess surface of a concave mold such that corners or edges of the semiconductor die are unconstrained or are the only portions of the semiconductor die in physical contact with the concave mold. The semiconductor die can include through-die cut lines that can lead to substantially less tension in the semiconductor die as compared to the case where the semiconductor die does not include through-die cut lines. Accordingly, such through-die cut lines can allow for achieving relatively large curvatures.


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