The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Oct. 10, 2016
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, Hubei, CN;

Inventors:

Lulu Xie, Guangdong, CN;

Bin Xiong, Guangdong, CN;

Yun Han, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 27/12 (2006.01); H05K 1/18 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1237 (2013.01); H01L 27/1259 (2013.01); H01L 29/4908 (2013.01); H01L 29/66143 (2013.01); H05K 1/189 (2013.01);
Abstract

A TFT array substrate and its manufacturing method are disclosed. The TFT array substrate includes a substrate having a display area and a non-display area, and at least a Schottky diode on the non-display area. The Schottky diode includes an anode layer and a cathode layer on the substrate, a gate insulation layer on the substrate covering the anode and cathode layers, a first gate on the gate insulation layer covering portions of the anode and cathode layers, an inter-layer insulation layer on the gate insulation layer covering the first gate and having a number of vias exposing the anode and cathode layers, respectively, and a first electrode and a second electrode in the vias on the inter-layer insulation layer connecting the anode and cathode layers, respectively. The present disclosure achieves simplified manufacturing process and reduced cost by forming the Schottky diode simultaneously when the TFT is formed.


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