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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10062707 B1

PDFFull Text
Date of Patent:
Aug. 28, 2018

Filed:

May. 22, 2017

Semiconductor device and method of manufacturing the same

Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Hyun Ho Lee, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:

William Park & Associates Ltd.

Primary Examiner:

Kimberly Rizkallah

Assistant Examiner:

Bo Bin Jang

Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 27/24 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 45/00 (2006.01); H01L 27/115 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02639 (2013.01); H01L 21/28282 (2013.01); H01L 27/249 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/42348 (2013.01); H01L 29/518 (2013.01); H01L 45/06 (2013.01);
Abstract

Provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer. The semiconductor device may also include an interlayer source layer configured to fill the source area.

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