The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Apr. 06, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Seok-Han Park, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 27/108 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/324 (2013.01); H01L 21/76229 (2013.01); H01L 21/76232 (2013.01); H01L 27/10805 (2013.01); H01L 27/10897 (2013.01); H01L 21/022 (2013.01); H01L 21/02222 (2013.01); H01L 21/02326 (2013.01); H01L 21/3086 (2013.01); H01L 21/32105 (2013.01);
Abstract

A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transformed into a second oxide layer and a third oxide layer, respectively, in the first trench, resulting in a semiconductor device with an isolation structure with good isolation characteristics.


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