The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Nov. 01, 2016
Applicant:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Inventors:

Steven B. Shauck, Crofton, MD (US);

Gary L. Phifer, Harleysville, PA (US);

Assignee:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 3/38 (2006.01); G06N 99/00 (2010.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 17/5031 (2013.01); G06F 17/5081 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 2217/06 (2013.01); G06N 99/002 (2013.01); H03K 3/38 (2013.01);
Abstract

One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.


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