The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2018
Filed:
Mar. 15, 2017
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Kejen Lin, Yokohama, JP;
Tokumasa Hara, Kawasaki, JP;
Hironori Uchikawa, Fujisawa, JP;
Juan Shi, Yokohama, JP;
Akira Yamaga, Kawasaki, JP;
Sho Kodama, Kawasaki, JP;
Keiri Nakanishi, Kawasaki, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/00 (2013.01); G11C 11/56 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/349 (2013.01); G11C 16/3459 (2013.01);
Abstract
According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.