The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Sep. 23, 2015
Applicant:

Hanan Potash, Austin, TX (US);

Inventor:

Hanan Potash, Austin, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 12/0815 (2013.01); G06F 2212/621 (2013.01);
Abstract

A computing device with multi-layer control: mentor layer and instruction/control layer includes a memory and one or more functional units. The computing device is configured to implement a multi-layer control structure including a data structure layer including a local high speed memory, a mentor layer, and an instruction/control layer. The local high speed memory includes one or more variables. The mentor layer includes one or more mentor circuits. The mentor circuits control actions associated with the Variables in the local high speed memory. The instruction/control layer includes one or more control circuits that interpret instructions or control operations by one or more functional units. In some embodiments, the local high speed memory implements a frame/bins structure. In some embodiments plural information is included in HLL and/or machine language.


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