The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Apr. 07, 2017
Applicant:

Realtek Singapore Pte Ltd, Singapore, SG;

Inventors:

Charles Chen, Fremont, CA (US);

Ryan Patrick Donohue, Sunnyvale, CA (US);

Donggun Keung, Milpitas, CA (US);

Xi Chen, Fremont, CA (US);

Xiaochong Cao, Fremont, CA (US);

Zeineddine Chair, Redwood City, CA (US);

Assignee:

REALTEK SINGAPORE PTE LTD, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); H04L 29/06 (2006.01); G06F 13/38 (2006.01); H04L 29/08 (2006.01); G06F 9/50 (2006.01); G06F 13/12 (2006.01); H04L 12/865 (2013.01);
U.S. Cl.
CPC ...
H04L 69/08 (2013.01); G06F 9/50 (2013.01); G06F 13/128 (2013.01); G06F 13/385 (2013.01); H04L 29/06 (2013.01); H04L 69/12 (2013.01); H04L 69/321 (2013.01); H04L 47/6275 (2013.01);
Abstract

Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware. In one implementation, a processing architecture includes a main processor configured to execute a first portion of a driver software to perform protocol control and management task associated with control or management packets in a packet-based protocol according to which packets are received from a device, an offload processor configured to execute a second portion of the driver software to perform data processing task for data packets received according to the packet-based protocol, an interface to enable communication with the device, and an interconnect coupled to the main processor, to the offload subsystem, and to the interface.


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