The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Mar. 24, 2016
Applicants:

Rajesh Jayashankara Shridevi, Bengaluru, IN;

Dean Michael Ancajas, Austin, TX (US);

Koushik Chakraborty, Logan, UT (US);

Sanghamitra Roy, Logan, UT (US);

Inventors:

Rajesh Jayashankara Shridevi, Bengaluru, IN;

Dean Michael Ancajas, Austin, TX (US);

Koushik Chakraborty, Logan, UT (US);

Sanghamitra Roy, Logan, UT (US);

Assignee:

Utah State University, Logan, UT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); H04L 29/06 (2006.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
H04L 63/1416 (2013.01); H04L 63/1458 (2013.01); H04L 49/109 (2013.01);
Abstract

For runtime detection of a bandwidth denial attack from a rogue NoC. The apparatus includes a processor and a memory storing code executable by the processor. The processor generates a plurality of proximal analogous packets each corresponding to a given packet traversing a multiprocessor system-on-chips (MPSoC). Each proximal analogous packet includes one or more of a proximal source modified from a given packet source and a proximal destination modified from a given packet destination. The processor further compares traversal latencies between each proximal analogous packet/given packet pair. In addition, the processor detects a rogue interconnect in response to aggregate variations in the traversal latencies.


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