The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Dec. 29, 2016
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Germano Nicollini, Piacenza, IT;

Roberto Modaffari, Pallanzeno, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/24 (2006.01); H03F 3/45 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/2481 (2013.01); G01R 19/0038 (2013.01); H03F 3/45179 (2013.01); H03F 3/45273 (2013.01);
Abstract

A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which includes a first load transistor and a first output transistor; and a second current mirror, which includes a second load transistor and a second output transistor. The comparator circuit further includes: a first feedback transistor and a second feedback transistor cross-coupled together, the control terminals of the first and second feedback transistors being connected to the first and second nodes, respectively; a first resistor, having a first terminal, which is connected to the control terminal of the first load transistor, and a second terminal, which is connected to the first node and to the control terminal of the first output transistor; and a second resistor, having a first terminal, connected to the control terminal of the second load transistor, and a second terminal, connected to the second node and to the control terminal of the second output transistor.


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