The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Jan. 31, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Seong Hoon Jeong, Seongnam-si, KR;

Hong Bum Park, Seoul, KR;

HanMei Choi, Seoul, KR;

Jae Young Park, Yongin-si, KR;

Seung Hyun Lim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/41 (2006.01); H01L 27/08 (2006.01); H01L 27/10 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7854 (2013.01); H01L 21/28158 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 29/0657 (2013.01); H01L 29/408 (2013.01); H01L 29/42364 (2013.01); H01L 29/513 (2013.01); H01L 29/7851 (2013.01); H01L 29/7853 (2013.01);
Abstract

A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.


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