The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Sep. 30, 2016
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Sik Lui, Sunnyvale, CA (US);

Hong Chang, Saratoga, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/26513 (2013.01); H01L 21/28035 (2013.01); H01L 21/3081 (2013.01); H01L 21/31144 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/4916 (2013.01); H01L 29/66613 (2013.01); H01L 29/78 (2013.01);
Abstract

Aspects of the present disclosure discloses a method for fabricating a trench MOSFET device comprising simultaneously forming a narrow trench and a wide trench into a semiconductor substrate using a mask to defines the narrow trench and the wide trench, forming an insulating layer over the semiconductor substrate with a first portion that fills up the narrow trench and a second portion that partially fills the wide trench, removing the second portion from the wide trench completely and leaving the narrow trench filled with the first portion, forming a gate electrode, forming a body region in a top portion of the semiconductor substrate, forming a source region in a portion of the body region, removing the first portion of nitride from the narrow trench, and forming a contact plug by filling a second conductive material in the narrow trench.


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