The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Aug. 04, 2017
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Tomohiro Hayashi, Tokyo, JP;

Hiraku Chakihara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/785 (2013.01);
Abstract

Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.


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