The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Jan. 05, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Manoj Kumar, Dhanbad, IN;

Hsiung-Shih Chang, Taichung, TW;

Pei-Heng Hung, New Taipei, TW;

Chia-Hao Lee, New Taipei, TW;

Jui-Chun Chang, Hsinchu, TW;

Chih-Cherng Liao, Jhudong Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/225 (2006.01); H01L 21/324 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 29/872 (2006.01); H01L 29/47 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2253 (2013.01); H01L 21/26513 (2013.01); H01L 21/28537 (2013.01); H01L 21/324 (2013.01); H01L 29/0649 (2013.01); H01L 29/47 (2013.01); H01L 29/66143 (2013.01); H01L 29/872 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.


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