The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Mar. 07, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Keiji Ikeda, Kawasaki, JP;

Chika Tanaka, Fujisawa, JP;

Toshinori Numata, Yokkaichi, JP;

Tsutomu Tezuka, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/24 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.


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