The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Aug. 28, 2017
Ningbo University, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Daohui Gong, Zhejiang, CN;
Yuejun Zhang, Zhejiang, CN;
Yaopeng Kang, Zhejiang, CN;
Ningbo University, Zhejiang, CN;
Abstract
The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1CNFET transistor, a 2CNFET transistor, a 3CNFET transistor, a 4CNFET transistor, a 5CNFET transistor, a 6CNFET transistor, a 7CNFET transistor, an 8CNFET transistor, a 9CNFET transistor, a 10CNFET transistor and an 11CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.