The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Mar. 01, 2017
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Guseul Baek, Ota Tokyo, JP;
Toshikazu Fukuda, Yokohama Kanagawa, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/417 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 5/14 (2013.01); G11C 5/147 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract
A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.