The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Apr. 22, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

HwaYoung Kim, Paju-si, KR;

ByungMu Jung, Goyang-si, KR;

SangSoo Han, Paju-si, KR;

SungJoon Moon, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H01L 27/32 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); H01L 27/3276 (2013.01); G09G 3/3266 (2013.01); G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01);
Abstract

A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.


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