The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Oct. 19, 2012
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Charles Joseph Tabony, Austin, TX (US);

Erich James Plondke, Austin, TX (US);

Lucian Codrescu, Austin, TX (US);

Suresh K. Venkumahanti, Austin, TX (US);

Evandro Carlos Menezes, Austin, TX (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/38 (2018.01); G06F 9/32 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30189 (2013.01); G06F 9/30054 (2013.01); G06F 9/30076 (2013.01); G06F 9/30149 (2013.01); G06F 9/30181 (2013.01); G06F 9/322 (2013.01); G06F 9/3816 (2013.01);
Abstract

Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.


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