The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Feb. 02, 2015
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Jin Quan Shen, Singapore, SG;

Yong Peng Chng, Singapore, SG;

Caihua Zheng, Singapore, SG;

Choon Kiat Tan, Singapore, SG;

Assignee:

SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/16 (2006.01); G06F 1/32 (2006.01); G06F 9/4401 (2018.01); G06F 3/0362 (2013.01); G06F 11/07 (2006.01); G06F 21/64 (2013.01); G11C 11/406 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/3268 (2013.01); G06F 1/3287 (2013.01); G06F 12/16 (2013.01); G06F 21/64 (2013.01); G11C 11/40615 (2013.01); G06F 3/0632 (2013.01); G06F 9/4401 (2013.01); G06F 11/0751 (2013.01); Y02D 10/14 (2018.01); Y02D 10/154 (2018.01); Y02D 50/20 (2018.01);
Abstract

An implementation of a system disclosed herein provides an apparatus, comprising a system on chip, wherein the system on chip is configured to receive a sleep command from a host and in response to the sleep command, calculate a primary checksum of a block of data from a low latency memory such as a tightly coupled memory (TCM), copy the primary checksum and the block of data into a volatile storage media, preserve interface variables of the system on chip in the volatile storage media, operate the volatile storage media in a self-refresh mode, and shut down power to other components on the system on chip.


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