The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Dec. 03, 2012
Applicant:

At&s Austria Technologie & Systemtechnik Aktiengesellschaft, Leoben, AT;

Inventors:

Markus Leitgeb, Trofaiach, AT;

Gerald Weidinger, Leoben, AT;

Gerhard Schmid, Trofaiach, AT;

Ljubomir Mareljic, Shanghai, CN;

Volodymyr Karpovych, Graz, AT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4697 (2013.01); H05K 3/0044 (2013.01); H05K 3/4691 (2013.01); H05K 2201/09127 (2013.01); H05K 2203/0191 (2013.01); H05K 2203/0264 (2013.01); Y10T 29/49156 (2015.01);
Abstract

Methods for the production of a circuit board involving the removal of a subregion in accordance with various embodiments of the invention are disclosed. In one embodiment, the production of a circuit board, made of at least two interconnected layers of material, involving the removal of a subregion including a portion of at least one of the at least two interconnected layers from the circuit board includes providing an adhesion preventing material under the subregion to be removed to a layer in the at least two interconnected layers that is adjacent to the at least one layer including the subregion, separating edge regions of the subregion to be removed from adjoining regions of the circuit board, connecting an external surface of the subregion to be removed to an external element, and displacing the external element to separate the subregion to be removed from the adjacent layer of the circuit board.


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