The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Mar. 10, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Giby Samson, San Diego, CA (US);

Yu Pu, San Diego, CA (US);

Kendrick Hoy Leong Yuen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03K 5/135 (2006.01); H03K 19/00 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); G06F 1/10 (2013.01); H03K 19/0016 (2013.01); H03K 2005/00052 (2013.01);
Abstract

Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.


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