The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Jul. 21, 2016
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Daisuke Shibata, Kyoto, JP;

Kenichiro Tanaka, Osaka, JP;

Masahiro Ishida, Osaka, JP;

Shinichi Kohda, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/417 (2006.01); H01L 29/20 (2006.01); H01L 29/861 (2006.01); H01L 29/872 (2006.01); H01L 29/205 (2006.01); H01L 29/04 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7788 (2013.01); H01L 29/045 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/41741 (2013.01); H01L 29/7789 (2013.01); H01L 29/861 (2013.01); H01L 29/872 (2013.01); H01L 29/1066 (2013.01); H01L 29/42316 (2013.01);
Abstract

A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.


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