The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Dec. 11, 2016
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Jack Wong, Phoenix, AZ (US);

Sajid Kabeer, Tempe, AZ (US);

Mel Hymas, Camas, WA (US);

Santosh Murali, Phoenix, AZ (US);

Brad Kopp, Beaverton, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02318 (2013.01); H01L 21/02323 (2013.01); H01L 21/02337 (2013.01); H01L 21/28273 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/7881 (2013.01);
Abstract

Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.


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